1. Field of the Invention
This invention relates to a semiconductor memory device, specifically relates to an error-detecting function thereof.
2. Description of Related Art
A NAND-type flash memory is known as one of EEPROMs (Electrically Erasable and Programmable ROMs). In a NAND-type flash memory, the memory cell array is formed of NAND cell units, each of which has plural memory cells connected in series. Since the unit cell area of the NAND cell unit is smaller than that of NOR-type cell array, it is easy to increase the memory capacitance.
Recently, to achieve a flash memory with a larger capacitance, there have been provided various multi-value storage schemes, in which one memory cell stores multi bits (for example, refer to Unexamined Japanese Patent Application Publication No. 2001-93288).
Further, to assure the reliability of a flash memory, there has been provided a technique for combining an ECC circuit with the memory (for example, refer to Unexamined Japanese Patent Application Publication No. 2002-251884).
A flash memory with a four-value data storage scheme has in general a smaller data margin (i.e., threshold distribution difference) in comparison with one of a binary data storage scheme because it is in need of setting four threshold voltage distributions. To achieve an eight-value or sixteen-value flash memory, the data margin will be further smaller. Therefore, if an ECC circuit is usually used one that is adaptable for a small number of bit errors, it may be impossible to be adapted to a flash memory with a multi-value data storage scheme.